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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33981 Rev 2.0, 10/2004
Preliminary Information High-Frequency, High-Current, Self-Protected High-Side Switch (4.0 m up to 60 kHz)
The 33981 is a high-frequency, self-protected 4.0 m RDS(ON) high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33981 can be controlled by pulse-width modulation (PWM) with a frequency up to 60 kHz. It is designed for harsh environments, and it includes self-recovery features. The 33981 is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. The 33981 is packaged in a 12 x 12 nonleaded power-enhanced Power QFN package with exposed tabs. Features * Single 4.0 m RDS(ON) Maximum High-Side Switch * * * * * * * * PWM Capability up to 60 kHz with Duty Cycle from 5% to 100% Very Low Standby Current Slew Rate Control with External Capacitor Overcurrent and Overtemperature Protection, Undervoltage Shutdown and Fault Reporting Reverse Battery Protection Gate Drive Signal for External Low-Side N-Channel MOSFET with Protection Features Output Current Monitoring Temperature Feedback
33981
HIGH-SIDE SWITCH 4.0 m
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Bottom View
16-TERMINAL PQFN (12 X 12)
SCALE 1:1 CASE 1402-02
PNA SUFFIX
ORDERING INFORMATION
Device PC33981PNA/R2 Temperature Range (TA) -40C to 125C Package 16 PQFN
Simplified Application Diagram 33981 Simplified Application Diagram
VDD
VDD 33981 SR CONF FS INLS EN INHS TEMP CSNS OCLS
VPWR VPWR CBOOT OUT DLS
I/O I/O MCU I/O I/O A/D A/D
GLS GND
M
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc. 2004
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VPWR
Undervoltage Detection
TEMP
Temperature Feedback
Bootstrap Supply
CBOOT
SR FS EN INHS
Logic Current Protection 100 A Overtemperature Detection 5.0 V RDWN ICONF IDWN CrossConduction
Gate Driver Slew Rate Control
OUT
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INLS
OUT Current Recopy 1/20000 Low-Side Gate Driver and Protection
GLS DLS
5.0 V
CONF
IOCLS
GND
CSNS
OCLS
Figure 1. 33981 Simplified Internal Block Diagram
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Transparent Top View of Package
CSNS TEMP EN INHS FS INLS CONF OCLS DLS GLS SR CBOOT 1 2 3 4 5 13 6 7 GND 8 9 10 11 12
16 14 VPWR
OUT
15
OUT
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TERMINAL DEFINITIONS Functional descriptions of some of these terminals can be found in the System/Application Information section beginning on page 19.
Terminal 1 Terminal Name CSNS Formal Name Output Current Monitoring Definition This terminal is used to output a current proportional to the high-side OUT current and is used externally to generate a ground-referenced voltage for the microcontroller (MCU) to monitor OUT current. This terminal reports an analog value proportional to the temperature of the GND flag (terminal 13). It is used by the MCU to monitor board temperature. This is an input used to place the device in a low current sleep mode. This terminal has an passive internal pulldown. The input terminal is used to directly control the OUT. This input has an active internal pulldown current source and requires CMOS logic levels. This is an open drain-configured output requiring an external pull-up resistor to VDD (5.0 V) for fault reporting. When a device fault condition is detected, this terminal is active LOW. The input terminal is used to directly control an external low-side N-channel MOSFET and has an active internal pulldown current source and requires CMOS logic levels. It can be controlled independently of the INHS depending of CONF terminal. This input terminal is used to manage the cross-conduction between the internal highside N-channel MOSFET and the external low-side N-channel MOSFET. The terminal has an active internal pullup current source. When CONF is at 0 V, the two MOSFETs are controlled independently. When CONF is at 5.0 V, the two MOSFETs cannot be on at the same time. This terminal sets the VDS protection level of the external low-side MOSFET. This terminal has an active internal pullup current source. It must be connected to an external resistor. This terminal is the drain of the external low-side N-channel MOSFET. Its monitoring allows for protection features. This terminal is an output used to drive the gate of the external low-side N-channel MOSFET. A capacitor connected between this terminal and the ground is used to control the output slew rate.
2 3 4 5
TEMP EN INHS
Temperature Feedback Enable (Active High) Serial Input High Side Fault Status (Active Low)
FS
6
INLS
Serial Input Low Side
7
CONF
Configuration Input
8
OCLS
Low-Side Overload
9 10 11
DLS GLS SR
Drain Low Side Low-Side Gate Slew Rate Control
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TERMINAL DEFINITIONS (continued) Functional descriptions of some of these terminals can be found in the System/Application Information section beginning on page 19.
Terminal 14 Terminal Name VPWR Formal Name Positive Power Supply Definition This terminal connects to the positive power supply and is the source input of operational power for the device. The VPWR terminal is a backside surface mount tab of the package. Protected high-side power output to the load. Output terminals must be connected in parallel for operation.
15, 16
OUT
Output
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit
ELECTRICAL RATINGS
Power Supply Voltage Steady-State Input/Output Terminals Voltage (Note 1) Output Voltage Continuous Output Current (Note 2) CSNS Input Clamp Current VIN VOUT IOUT ICSNS VSR VTEMP CBOOT VOCLS VGLS VDLS VESD1 VESD2 ECL VPWR -16 to 41 -0.3 to 7.0 -5.0 to 41 40 10 -0.3 to 54 -0.3 to 5.0 -0.3 to 54 -0.3 to 7.0 -0.3 to 15 -5.0 to 41 2000 200 TBD J V V A mA V V V V V V V V
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SR Voltage Temperature Feedback Voltage CBOOT Voltage OCLS Voltage Low-Side Gate Voltage Low-Side Drain Voltage ESD Voltage Human Body Model (Note 3) Machine Model (Note 4) Output Clamp Energy (Note 5)
THERMAL RATINGS
Operating Temperature Ambient Junction Storage Temperature Thermal Resistance (Note 6) Junction to Power Die Case Junction to Ambient Peak Terminal Reflow Temperature During Solder Mounting (Note 7) Power Dissipation (TA = 25C) (Note 8) RJC RJA TSOLDER PD 1.0 20 240 TBD C W C
TA TJ
TSTG
-40 to 125 -40 to 150 -55 to 150
C C/W
Notes 1. Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN terminals may cause a malfunction or permanent damage to the device. 2. Continuous high-side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 4. 5. 6. 7. 8. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ) and in accordance with the system module specification with a capacitor > 0.01 F connected from OUT to GND. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150C). Device mounted on a 2s2p test board per JEDEC JESD51-2. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used.
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
Battery Supply Voltage Range Fully Operational Extended VPWR Supply Current Output ON, IOUT = 0 A VPWR Supply Current IPWR(SBY) - IPWR(SLEEP) - - VPWR(UV) VPWR(UVHYS) 2.0 - - - - 0.3 5.0 50 4.0 - V V - 10 A IPWR(ON) - - 10 mA VPWR 6.0 4.5 - - 27 27 mA V
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Output OFF, EN = 5.0 V, OUT Connected to GND Sleep State Supply Current (VPWR < 14 V, EN = 0 V) TJ = 25C TJ = 125C Undervoltage Shutdown Undervoltage Hysteresis
POWER OUTPUT
Output Drain-to-Source ON Resistance (IOUT = 20 A, TJ = 25C) VPWR = 6.0 V VPWR = 10.0 V VPWR = 13 V Output Drain-to-Source ON Resistance (IOUT = 20 A, TJ = 150C) VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V Output Drain-to-Source ON Resistance (IOUT = 20 A, TJ = 25C) VPWR = - 13 V Output Overcurrent Detection Level Current Sense Ratio 9.0 V < VPWR < 16 V, CNS < 4.5V Current Sense Ratio (CSR) Accuracy Output Current 5.0 A 10 A 30 A Current Sense Voltage Clamp I CCNS = 15 mA VCL(CSNS) 4.5 6.0 7.0 CSR_ACC -20 -14 -12 - - - 20 14 12 V I OCH CSR - 1/20000 - % RDS(ON) - - - - 8.0 100 A - RDS(ON) - - - - - - 10.2 8.5 6.8 m RDS(ON) - - - - - - 6.0 5.0 4.0 m m
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT (continued)
Overtemperature Shutdown Overtemperature Shutdown Hysteresis (Note 9) Low-Side Gate VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V VPWR = 27 V Low-Side Gate Current C = 4.7 nF Low-Side Overload Detection Level versus Low-Side Drain Voltage VOCLS - VDLS Temperature Feedback TJ = 25C Temperature Feedback Derating DTFeed TFeed TBD - 4.75 -12 TBD - mV/C VDS_LS - - 50 V I GSLS - 100 - mV TSD TSD(HYS) VGSLS - - - - 6.0 9.0 12 12 - - - - mA 160 5.0 175 - 190 20 C
C
V
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CONTROL INTERFACE
Input Logic High Voltage (Note 10) Input Logic Low Voltage (Note 10) Input Logic Voltage Hysteresis (Note 10) Input Logic Active Pulldown Current (INHS, INLS) Input Logic Pulldown Resistor (EN) Input Active Pullup Current (OCLS) Input Active Pullup Current (CONF)
FS Tri-State Capacitance (Note 9) FS Low-State Output Voltage
VIH VIL VIN(HYS) IDWN RDWN IOCLSp I CONF CSO VSOL
0.7 - 100 5.0 100 - - - -
- - 350 - 200 100 10 - 0.2
- 0.2 750 20 400 - - 20 0.4
VDD VDD mV A k A A pF V
Notes 9. Parameter is guaranteed by process monitoring but is not production tested. 10. Upper and lower logic threshold voltage range applies to EN, CONF, INHS, and INLS input signals.
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
CONTROL INTERFACE AND POWER OUTPUT TIMING
CBOOT Charge Blanking Time (Note 11) Output Rising Slew Rate (Note 12) VPWR = 14 V CGATE = 6.8 nF, from 10% to 90% of VOUT, SR Capacitor = 4.7 nF Output Falling Slew Rate (Note 12) VPWR = 14 V CGATE = 6.8 nF, from 90% to 10% of VOUT, SR Capacitor = 4.7 nF Output Turn-ON Delay Time (Note 13) Output Turn-OFF Delay Time Input Switching Frequency (Note 14) SRF - - 25 - 200 400 - - - - - 60 ns ns kHz
t ON
SRR
-
20
-
s V/s
- -
25 -
- - V/s
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t DLY(ON) t DLY(OFF)
f PWM
- - -
Notes 11. Refer to the paragraph entitled Sleep Mode on page 19. 12. Parameter is guaranteed by process monitoring but is not production tested. 13. Turn-ON delay time measured from rising edge of INHS that turns the output ON to VOUT = 0.5 V with RL= 5.0 resistive load. 14. Turn-OFF delay time measured from falling edge of INHS that turns the output OFF to VOUT = VPWR -0.5 V with RL= 5.0 resistive load.
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Table 1. Functional Truth Table in Normal Mode
Condition Sleep Normal CONF INHS x L x H INLS x H OUT x H GLS x H
FS
EN L H
Comments Device is in Sleep mode. The OUT and low-side gate are OFF. Normal mode. High side and low side are controlled independently. The high side and the low side are both on. Normal mode. High side and low side are controlled independently. The high side and the low side are both off. Normal mode. No cross-conduction. Halfbridge configuration. The high side is off and the low side is on. Normal mode. No cross-conduction. Halfbridge configuration. The high side is on and the low side is off. Normal mode. Cross-conduction management is activated. Half-bridge configuration.
H H
Normal
L
L
L
L
L
H
H
Normal
H
L
H
L
H
H
H
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Normal
H
H
L
H
L
H
H
Normal
H
PWM
H
PWM
PWM OR H (Logical OR)
H
H
H = High level L = Low level x = Don't care PWM = Pulse-width modulation
Table 2. Functional Truth Table in Fault Mode
Conditions Overtemperature on OUT CONF x INHS x INLS x OUT L GLS x
FS
EN H
TEMP CSNS OCLS L x x
Comments The 33981 is currently in fault mode. The OUT is OFF. TEMP at 0 V indicates this fault. Once the fault is removed 33981 recovers its normal mode. The 33981 is currently in fault mode. The OUT is OFF and GLS is at 0 V. TEMP at 0 V indicates this fault. Once the fault is removed 33981 recovers its normal mode. The 33981 is currently in fault mode. The OUT is OFF. It is reset by a logic [0] at INHS for at least 200 s. When INHS goes to 0 V, CSNS goes to 5.0 V. The 33981 is currently in fault mode. GLS is at 0 V and OCLS internal current source is off. The external resistance connected between OCLS and GND terminal will pull OCLS terminal to 0 V. The fault is reset by a logic [0] at INLS for at least 200 s.
L
Overtemperature on CBOOT or GLS
x
x
x
L
L
L
H
L
x
x
Overcurrent on OUT
x
H
x
L
x
L
H
x
L
x
Overload on External LowSide MOSFET
L
x
H
x
L
L
H
x
x
L
H = High level L = Low level x = Don't care
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Timing Diagram
INHS
VPWR - 0.5 V 0.5 V OUT
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t DLY(ON)
t DLY(OFF)
Figure 2. Time Delays
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Functional Diagrams
EN CONF
0V
INHS
High Side ON
High Side OFF
INLS
Low Side ON
Thermal Shutdown on OUT
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OUT
0V
GLS Thermal Shutdown on OUT FS Thermal Shutdown on OUT
5.0 V 0V
Thermal Shutdown on OUT
5.0 V 0V
Thermal Shutdown on OUT
TEMP
0V
Thermal Shutdown on OUT High Side ON TSD Thermal Shutdown on OUT High Side OFF TSD Hysteresis
Temperature OUT
Hysteresis
Figure 3. Overtemperature on Output
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EN CONF
0V
High Side ON
INHS
High Side OFF
INLS
Low Side ON Thermal Shutdown on Bootstrap Circuit or on Low-Side Gate Drive
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OUT
0V
Thermal Shutdown GLS Thermal Shutdown FS
0V
Thermal Shutdown
5.0 V 0V
Thermal Shutdown 15 s After
0V
Thermal Shutdown
15 s After
TEMP Thermal Shutdown Thermal Shutdown
Temperature Control
TSD
Hysteresis
TSD
Hysteresis
Figure 4. Overtemperature on Bootstrap Circuit or on Low-Side Gate Drive
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EN
INLS
0V 200 s Min
Overload on Low Side
GLS
0 V Low Side OFF
Overload on Low Side
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5.0 V
FS
0V
Overload on Low Side
OCLS Overload on Low Side
VDS_LS = VOCLS
0V
VDS_LS
Case 1: Overload Removed
Figure 5. Overload on Low-Side Gate Drive, Case 1
EN
INLS
0V
200 s Min Overload on Low Side
GLS
0 V Low Side OFF
Overload on Low Side
FS
0V
Overload on Low Side
OCLS Overload on Low Side
VDS_LS = VOCLS
0V
VDS_LS
Case 2: Low Side Still Overloaded
Figure 6. Overload on Low-Side Gate Drive, Case 2
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EN
INHS
0V 200 s Min
Overcurrent on High Side
OUT
0V
Overcurrent on High Side
5.0 V
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FS Overcurrent on High Side
0V 5.0 V
CSNS
0V
Overcurrent on High Side IOCH Fault Removed
IOUT
Figure 7. Overcurrent on Output
EN
FS
15 s After 5.0 V
CONF
INHS
INLS
OUT
GLS
Figure 8. Normal Mode. Cross-Conduction Management
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EN
FS CONF
15 s After
0V
INHS
High Side ON
High Side OFF
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INLS
OUT
GLS
Figure 9. Normal Mode. Independent High Side and Low Side
INHS
IOUT Io ut
CSNS CSNS
FS FS
Figure 10. High-Side Overcurrent
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INHS
GLS
Iout
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Current in Motor
Recirculation in Low Side
OUT
Figure 11. Cross-Conduction with Low Side Overtemperature INHS
TEMP
OUT IOUT
Figure 12. Overtemperature on OUT
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EN
TEMP
Overtemperature OUT
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IOUT
Figure 13. Overtemperature on Bootstrap Circuit or on Low-Side Gate Drive
Figure 14. Maximum Operating Frequency for SR Capacitor of 4.7 nF
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Electrical Performance Curves
7.0 6.0
RDS(ON) (m) RdsON (mOhm)
5.0 4.0 3.0 2.0 1.0 0.0 -50 0 50 100 150 200
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Temperature (C) Temperature (C) Figure 15. RDS(ON) versus Temperature
10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 4.5 6.0 9.0 12.0 12.5
VPWR (V) Vpwr(V) Figure 16. Sleep State Supply Current versus VPWR at 150C
IIpwr(sleep)(A) PWR(SLEEP) (A)
13.0
14.0
17.0
21.0
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33981 is a high-frequency self-protected silicon 4.0 m RDS(ON) high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33981 can be controlled by pulse-width modulation (PWM) with a frequency up to 60 kHz. It is designed for harsh environments, and it includes self-recovery features. The 33981 is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. A dedicated parallel input is available for an external low-side control with protection features and cross-conduction management.
FUNCTIONAL DESCRIPTION Sleep Mode
terminal transition to logic [1] will be disabled typically 15 s after to enable the charge of the bootstrap capacitor. Figure 13, page 17, shows an overtemperature on the bootstrap circuit or on the low-side gate drive. As the temperature increases, TEMP voltage decreases until thermal shutdown. Overtemperature faults force the TEMP terminal to 0 V.
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Sleep mode is the state of the 33981 when the EN is logic [0]. In this mode, OUT, the gate driver for the external MOSFET, and all unused internal circuitry are off to minimize current draw. The 33981 will go to the normal operating mode when the EN terminal is logic [1]. The INHS and INLS commands will be disabled typically 20 s after the EN transitions to logic [1] to enable the charge of the bootstrap capacitor.
Overcurrent Fault on High Side Fault Logic
This 33981 indicates the faults below as they occur by driving the FS terminal to logic [0]: * Overtemperature * Overcurrent fault on OUT * Overload fault on the external low-side MOSFET The FS terminal will return to logic [1] when the overtemperature fault condition is removed. The two other faults are latched. The OUT terminal has a 100 A overcurrent high-detection level for maximum device protection. If at any time the current reaches this level, OUT will stay OFF and the CSNS terminal will go to 0 V. The OUT terminal is reset by a logic [0] at the INHS terminal for at least 200 s. When INHS goes to 0 V, CSNS goes to 5.0 V. In Figure 11, page 16, the OUT terminal is short-circuited to 0 V. When the current reaches I OCH , OUT is turned OFF within 10 s owing to internal logic circuit.
Undervoltage
The latched faults are reset when the VPWR voltage is below VPWR(UV).
Overload Fault on Low Side
This fault detection is active when INLS is logic [1]. Low-side overload protection does not measure the current directly but rather its effects on the low-side MOSFET. When VGLS > VGSH and VDLS > VDSH for at least 2.5 s, the GLS terminal goes to 0 V and the OCLS internal current source is disconnected and OCLS goes to 0 V. The GLS terminal and the OCLS terminal are reset by a logic [0] at the INLS terminal for at least 200 s. When connected to an external resistor, the OCLS terminal with its internal current source sets the VDSH level. By changing the external resistance, the protection level can be adjusted depending on low-side characteristics. A 3.3 k resistor gives a VDSH level of 3.3 V typical. This protection circuitry measures the voltage between the drain of the low side (DLS terminal) and the 33981 ground (GND terminal). It also uses the voltage across the external resistance connected to the OCLS terminal and the GND terminal. For this reason it is key that the low-side source, the 33981 ground, and the external resistance ground connection are connected together in order to prevent false error detection due to ground shifts.
Overtemperature Fault
The 33981 incorporates overtemperature detection and shutdown circuitry on OUT. Overtemperature detection also protects the bootstrap circuit (CBOOT terminal) and the low-side gate driver (GLS terminal). Overtemperature detection occurs when OUT is in the ON or OFF state and GLS is at high or low level. For OUT, an overtemperature fault condition results in OUT turning OFF until the temperature falls below TSD. This cycle will continue indefinitely until the offending load is removed. Figure 12, page 16, shows an overtemperature on OUT. An overtemperature fault on the bootstrap circuit or on the low-side gate drive results in OUT turning OFF and the GLS going to 0 V until the temperature falls below TSD. This cycle will continue indefinitely until the offending load is removed. FS
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Configuration
The CONF terminal manages the cross-conduction between the internal MOSFET and the external low-side MOSFET. With the CONF terminal at 0 V, the two MOSFETs can be independently controlled. A load can be placed between the high side and the low side. With the CONF terminal at 5.0 V, the two MOSFETs cannot be on at the same time. They are in half-bridge configuration as shown in the simplified application diagram on page 1. If INHS and INLS are at 5.0 V at the same time, INHS has priority and OUT will be at VPWR. If INHS changes from 5.0 V to 0 V with INLS at 5.0 V, GLS will go to high state as soon as the VGS of the internal MOSFET is lower than TBD typically. A half-bridge application could consist in sending PWM signal to the INHS terminal and 5.0 V to the INLS terminal with the CONF terminal at 5.0 V. Figure 11, page 16, illustrates the simplified application diagram on page 1 with a DC motor and external low side. The CONF and INLS terminals are at 5.0 V. When INHS is at 5.0 V, current is flowing in the motor. When INHS goes to 0 V, the load current recirculates in the external low side.
Thermal Feedback
The 33981 has an analog feedback output (TEMP terminal) that provides a value proportional to the temperature of the GND flag (terminal 13). The controlling microcontroller can "read" the temperature proportional voltage with its analog-todigital converter (ADC). This can be used to provide real-time monitoring of the PC board temperature to optimize the motor speed and to protect the whole electronic system. TEMP terminal value is typically 4.2 V at 25C with a negative temperature coefficient of 10 mV/K.
Reverse Battery
The 33981 survives the application of reverse battery voltage as low as -16 V. Under these conditions, the output's gate is enhanced to decrease device power dissipation. No additional passive components are required. The 33981 survives these conditions until the maximum junction rating is reached. In the case of reverse battery in a half-bridge application, a direct current passes through the external freewheeling diode and the internal high-side. As Figure 17 shows, it is essential to protect this power line. The proposed solution is an external low-side with its gate tied to battery voltage through a resistor. A high-side in the VPWR line could be another solution but with a more complex drive.
VDD VPWR 33981 MCU
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Bootstrap Supply
Bootstrap supply provides current to recharge the bootstrap capacitor through the VPWR terminal. A short time is required after the application of power to the device to charge the bootstrap capacitor. A typical value for this capacitor is 100 nF. An internal charge pump allows continuous MOSFET drive. When the device is in the sleep mode, this bootstrap supply is off to minimize current consumption.
No current
GND
OUT
High-Side Gate Driver
The high-side gate driver switches the bootstrap capacitor voltage to the gate of the MOSFET. The driver circuit has a lowimpedance drive to ensure that the MOSFET remains OFF in the presence of fast falling dV/dt transients on the OUT terminal. This bootstrap capacitor connected between the power supply and the CBOOT terminal provides the high pulse current to drive the device. The voltage across this capacitor is limited to about 13 V. CBOOT is protected against short by a local overtemperature sensor. An external capacitor connected between terminals SR and GND is used to control the slew rate at the OUT terminal. Figure 17. Reverse Battery Protection
Diode
VPWR
M
Low-Side Gate Driver
The low-side control circuitry is PWM capable. It can drive a standard MOSFET with an RDS(ON) as low as 4.0 m at a frequency up to 60 kHz. The VGS is internally clamped at 14 V typically to protect the gate of the MOSFET. The GLS terminal is protected against short by a local overtemperature sensor.
33981 20
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
APPLICATIONS
Figure 18 shows a typical application for the 33981. A brush DC motor is connected to the output. A low-side gate driver is used for the freewheeling phase. Typical values for the external capacitors and resistances are given.
VDD VDD VPWR
33981
SR 1.0 k 2.2 nF CONF I/O
FS
VPWR CBOOT
330 F
100 nF OUT DLS
Freescale Semiconductor, Inc...
I/O I/O
INLS EN INHS TEMP CSNS 1.0 k OCLS 33 k
MCU
I/O A/D A/D
GLS GND
M
Figure 18. 33981 Typical Application Diagram
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33981 21
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
PNA SUFFIX 16-TERMINAL PQFN NONLEADED PACKAGE CASE 1402-02 ISSUE B
12
12 1 2X
A M 0.1 C
PIN 1 INDEX AREA
Freescale Semiconductor, Inc...
12
15
16
M PIN NUMBER REF. ONLY 0.1 C 2.2 2.20 2.0 1.95 0.05 C 4
B
2X
0.1 C
10X
0.6 0.2 0.1 0.05
DETAIL G
M M
0.05 0.00 DETAIL G
VIEW ROTATED 90 CLOCKWISE
C
SEATING PLANE
CAB C
9X
2X
0.95 0.55 0.1 0.05 1.1 0.6
M M
CAB C
1
0.9
2X 1.075
0.1 C A B 5.0 4.6
12
6X
6X
2.05 1.55
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. 5. MINIMUM METAL GAP SHOULD BE 0.25MM.
2.5 2.1 1.45 5.5 4X 1.05 5.1 0.1 C A B
13
3.55 1.85
14
(2)
6X
0.8 0.4 1.28 0.88
(10X 0.25) 2.25 1.75 (2X 0.75)
16
15 2X
(10X 0.4) 0.1 C A B
(0.5) (10X 0.5) 10.7 10.3 0.1 C A B 11.2 10.8 0.1 C A B VIEW M-M
0.15 0.05
6 PLACES
CASE 1402-02
33981 22
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
NOTES
Freescale Semiconductor, Inc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product, Go to: www.freescale.com
33981 23
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors
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